Three-level neutral point clamping pwn inverter and neutral point voltage controller

ABSTRACT

On the basis of: a first calculated value ic which is a product of a calculated value of a time of three-phase output voltages in a state where a positive bus, a negative bus, and a neutral line are connected respectively to three-phase phase output terminals, and a predicted neutral current value in the state; and second and third calculated values icx and icy which are products of a calculated value of a time of the three-phase output voltages that can take state 1 where two of the three-phase phase output terminals are connected to the positive bus or the neutral line, and a remaining one terminal is connected to the neutral line or the negative bus, and state 2 opposite to the state, and predicted neutral current values in states 1 and 2, a time ratio of state 1 and 2 during a PWM period is determined so as to make a current flowing through the neutral line close to zero, or a potential of the neutral line of the three-phase output voltages close to a voltage which is exactly the middle between voltages of the positive and negative busses.

TECHNICAL FIELD

[0001] The present invention relates to a three-levelneutral-point-clamped PWM inverter apparatus which is one of a powerconverter such as an inverter or a servo drive that speed-variablydrives a motor, and a power converter that interconnects systems, andalso to a neutral voltage controller which is used in such a three-levelneutral-point-clamped PWM inverter to control a neutral voltage that isa voltage between a neutral point of two capacitors connected in seriesbetween positive and negative busses of the apparatus, and the negativebus.

BACKGROUND ART

[0002]FIG. 1 is a circuit diagram showing the main circuit configurationof a three-level neutral-point-clamped PWM inverter apparatus. As shownin FIG. 1, the three-level neutral-point-clamped PWM inverter apparatusis configured by two capacitors 7, three-phase output terminals, twelveswitching elements 8, and eighteen diodes 9.

[0003] In the thus configured three-level neutral-point-clamped PWMinverter apparatus, when switching elements 8 ₁, 8 ₂ are turned on, theoutput terminals of the phases are connected to a positive bus which isconnected to a point P, and output phase voltages of the phases are at ahigh level. When switching elements 8 ₂, 8 ₃ are turned on, the outputterminals of the phases are connected to a point C which is the neutralpoint, and the output phase voltages of the phases are at anintermediate level (neutral voltage) which is between the high level anda low level. When switching elements 8 ₃, 8 ₄ are turned on, the outputterminals of the phases are connected to a negative bus which isconnected to a point N, and the output phase voltages of the phases areat the low level. In the three-level neutral-point-clamped PWM inverterapparatus, usually, the switching elements 8 are switched on the basisof the above-mentioned three patterns to drive a three-phase load.

[0004] In such a three-level neutral-point-clamped PWM inverterapparatus, the neutral voltage is obtained by voltage division of thecapacitors 7. The neutral voltage is varied in accordance with a currentsupplied to the load. When the neutral voltage is varied, an excessvoltage is applied to the capacitors 7, thereby causing the possibilitythat the capacitors 7 are shortened in life or broken. In a three-levelneutral-point-clamped PWM inverter apparatus, therefore, a neutralvoltage control is performed in order to suppress or control variationof the neutral voltage.

[0005] In a neutral voltage control of the thus configuredneutral-point-clamped PWM inverter, conventionally, the current flowingthrough the neutral line is controlled by using dipolar modulation orunipolar modulation as a method of generating PWM pulses, and increasingand decreasing the zero-sequence voltage of a voltage command.

[0006] On the other hand, as disclosed in JP-A-5-292754, when theconcept of a voltage vector is introduced and a PWM control isperformed, a method is usually employed in which a neutral voltagecontrol is performed while the increasing or decreasing direction of anintermediate voltage vector is determined from the sign of a load power.As proposed in JP-A-2001-57784, such a method includes that in which ageneration time ratio of a correction vector is finely adjusted inaccordance with the direction of a current flowing through a neutralline.

[0007] In these methods, variation of the neutral voltage is suppressedby, among twelve sets of switch states such as shown in FIG. 2,adjusting the ratio of paired switch states in which the output voltagesare equal to each other but the current directions of the neutral lineare opposite to each other.

[0008] As proposed in JP-A-2001-61283, there is also a method such asshown in FIG. 3 in which a switch state disturbing the neutral voltageis suppressed. When switch states which can be attained by aneutral-point-clamped PWM inverter are indicated in the form of outputvoltage vectors, they can be expressed as shown in FIG. 4.

[0009]FIG. 5 shows an example of an apparatus which calculates a PWMpulse of a neutral-point-clamped PWM inverter with using the concept ofa space voltage vector. The apparatus comprises a vector time calculator102, a vector time register 103, a PWM pulse pattern setting device 104,and a parameter setting device 105.

[0010] In the apparatus, it is assumed that an output voltage outputfrom the inverter is a space vector quantity such as shown in FIG. 4.When the modulation rate (k) and phase (θ) of an output voltage V aregiven, the vector time calculator 102 outputs the region of the outputvoltage vector V to the PWM pulse pattern setting device 104, selectsthe 27 kinds of vectors shown in FIG. 4, and calculates vector sequenceswhich are sequentially output and vector output times (T0-T5) as PWMpulses in which an average of PWM periods is equal to the output voltagevector V. The vector sequences and the vector output times (T0-T5) arestored in the vector time register 103. The vector sequences and vectoroutput times which are stored are converted by the PWM pulse patternsetting device 104 to a pulse sequence of U1, U2, V1, V2, W1, and W2which drive switch elements of an inverter main circuit. The switchelements of the inverter main circuit are turned on/off by the pulsesequence, and a desired voltage is output. In this apparatus, on thebasis of the neutral voltage from the parameter setting device 105 and asignal from a detector for a load power factor, the PWM pulse patternsetting device 104 adjusts the generation time of the correction vectorin a direction along which the variation of the neutral voltage isreduced.

[0011] JP-A-9-37592 discloses a method of PWM controlling a three-levelinverter in which a region between one long vector of output spacevectors of a three-level inverter, and a vector that is adjacent to thelong vector, and that has an intermediate length is set as one space.The whole space of 360° which is formed by these vectors is divided intotwelve regions. The region number of a command vector in the twelveregions is judged depending on the rotation angle of the command vector.The modulation rate is calculated in accordance with the degree of thecommand vector. The transmission system and the transmission sequencefor suppressing variation of the neutral voltage of voltage dividingcapacitors of the three-level inverter are determined in accordance withthe modulation rate and the current ratio. Specific output times of thevectors in the transmission system and the transmission sequence arecalculated to PWM control the three-level inverter.

[0012] As described above, in a three-phase neutral-point-clamped PWMinverter, usually, an even number of capacitors are directly connectedbetween positive and negative busses of a main circuit in order toobtain the neutral voltage, and a neutral line is used while being takenout from a capacitor terminal which has a voltage that is exactly themiddle voltage between the positive and negative busses. The neutralline is connected as shown in FIGS. 2 and 3 depending on the output loadof the PWM inverter and the switch states of the PWM inverter. Thevoltage of the neutral line (the neutral voltage) is varied inaccordance with the current which charges the capacitors through thepositive and negative busses, and that which is supplied from theconnected load.

[0013] As shown in the conventional art examples, in the switch statesshown in FIG. 3 (in the description, the vector is referred to as acorrection vector), a set of switch states in which the line voltage tobe output to the load is the same but the phase of the load connected tothe neutral line is different (adjacent switch states in FIG. 2 arebundled into one set) is used, and the time ratio in which the switchstates of the set are generated is adjusted, whereby the neutralpotential can be finely controlled.

[0014] In the switch states shown in FIG. 2 (in the description, thevector is referred to as an intermediate vector), however, the neutralvoltage is varied by the phase currents of the load connected to theneutral line and the time ratio in which the switch state is generated,and there is no vector which corrects the variation. Therefore, thevariation of the neutral voltage caused by an intermediate vector mustbe corrected with using a correction vector.

[0015] As shown in JP-A-2-261063, therefore, a zero-sequence voltage isadded to the modulation rate, the occurrence time of a correction vectoris adjusted, and the variation of the neutral voltage is controlledwithout changing the output line voltage which is to be supplied to aload. As shown in JP-A-5-292754 and JP-A-2001-57784, also in the methodwhich uses the concept of a space voltage vector, an output is conductedso that a correction vector is used in a voltage vector to be used, andthe occurrence time of the switch state of the set is adjusted tocontrol the neutral voltage. In these methods, however, the technique ofdetermining the ratio of the correction vector to make the neutralvoltage variation close to zero is not optimum, and the effect ofsuppressing the neutral voltage variation is insufficient.

[0016] In the method described in JP-A-9-37592, the transmission systemand the transmission sequence for suppressing variation of the neutralpotential of the voltage dividing capacitors of the predeterminedthree-level inverter are determined in accordance with the modulationrate and the current ratio, and specific output times of the vectors inthe transmission system and the transmission sequence are calculated toperform a PWM control. Therefore, it is possible to bring the neutralcurrent close to zero. In the method also, however, the neutral voltagevariation cannot be reduced completely to zero.

[0017]FIG. 6 is a block diagram showing the configuration of aconventional neutral voltage controller which detects the level of theneutral voltage and outputs a neutral voltage control command forsuppressing the neutral voltage variation. As shown in FIG. 6, theconventional neutral voltage controller is configured by two isolationamplifiers 6 and a calculation circuit 3.

[0018] A first reference voltage V_(ref1) which is one half of a voltageV_(PN) (DC bus voltage) between the point P and the point N, and avoltage between the point C and the point N, i.e., the neutral voltageV_(CN) are input to the two isolation amplifiers 6, respectively. Thecalculation circuit 3 receives outputs of the two isolation amplifiers6, calculates a neutral voltage control command for making the neutralvoltage VCN and the first reference voltage V_(ref1) coincident witheach other, and outputs the command. The neutral voltage control commandis a command to produce an output pattern of a PWM (Pulse WidthModulation) command for raising or lowering the value of the neutralvoltage.

[0019] As described above, in the neutral voltage controller, theneutral voltage VCN and the first reference voltage V_(ref1) are inputto the calculation circuit 3, and hence the two isolation amplifiers 6serving as insulation circuits are required. Such insulation circuitsare required because the calculation circuit 3 is usually driven by apower source which is different from that for the main circuit of theinverter.

[0020] However, the isolation amplifiers 6 are expensive analoginsulation circuits having a wide linear characteristic, and thereforehave a problem in that the neutral voltage controller is expensive. Inthe conventional neutral voltage controller, since the calculationcircuit 3 controls the neutral voltage on the basis of analog signals,there is a problem in that the apparatus is easily affected by noises orthe like.

DISCLOSURE OF THE INVENTION

[0021] It is an object of the invention to provide a three-phaseneutral-point-clamped PWM inverter apparatus in which the neutralpotential variation can be efficiently suppressed, and the safety andthe quality of the output voltage can be improved.

[0022] In order to attain the object, in the three-phaseneutral-point-clamped PWM inverter apparatus of the invention, a firstcalculated value which is a product of: a calculated value of a time ofthree-phase output voltages in a state where a positive bus, a negativebus, and a neutral line are connected respectively to three-phase phaseoutput terminals; and a predicted neutral current value in the state isobtained. Moreover, second and third calculated values which areproducts of: a calculated value of a time of the three-phase outputvoltages that can take state 1 where two of the three-phase phase outputterminals are connected to the positive bus or the neutral line, and aremaining one terminal is connected to the neutral line or the negativebus, and state 2 opposite to the state; and predicted neutral currentvalues in states 1 and 2 are obtained. Furthermore, on the basis of thefirst, second, and third calculated values, a time ratio of state 1 and2 during a PWM period is determined so as to make a current flowingthrough the neutral line close to zero, or a potential of the neutralline of the three-phase output voltages close to a potential which isexactly the middle between voltages of the positive and negative busses.

[0023] According to the configuration, the neutral potential variationcan be efficiently suppressed by making close to zero as far aspossible, or making the potential of the neutral line close to apotential which is exactly the middle between the potentials of thepositive and negative busses. Therefore, the safety and the quality ofthe output voltage can be improved.

[0024] It is another object of the invention to provide a neutralvoltage controller which is economical, and highly reliable andaccurate.

[0025] In order to attain the object, in the invention, a firstreference voltage value which is one half of a voltage between apositive bus and a negative bus is subtracted from a value of a neutralvoltage, when a result of the subtraction is smaller than a secondreference voltage value which is a negative value, a signal for raisingthe neutral voltage is turned on, when the result of the subtraction islarger than a third reference voltage value which is a positive value, asignal for lowering the neutral voltage is turned on, the two signalsare converted in an insulative manner to a 2-bit digital signal, and aneutral voltage control command is calculated on the basis of thedigital signal and then output.

[0026] According to the configuration, the differences between theneutral voltage and the reference voltage values are expressed by adigital signal instead of an analog signal, thereby enabling economicalinsulating means to be used without using expensive insulating meanshaving a wide linear characteristic. Therefore, the whole apparatus canbe economically configured. Since the differences between the neutralvoltage and the reference voltage values are processed in the form of adigital signal instead of an analog signal, an influence of noises on aninput to calculating means can be reduced. Therefore, it is possible toprovide a neutral voltage controller in which the reliability isenhanced, and which is highly accurate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1 is a circuit diagram showing a main circuit configurationof a three-level inverter apparatus;

[0028] FIGS. 2(a) to 2(1) shows the diagrams showing an example of setsof switch states of a three-phase neutral-point-clamped inverter;

[0029] FIGS. 3(a) to 3(f) show the diagrams showing an example of othersets of switch states of the three-phase neutral-point-clamped inverter;

[0030]FIG. 4 is a diagram of output voltage space vectors of athree-phase neutral-point-clamped inverter;

[0031]FIG. 5 is a block diagram of a conventional PWM pulse calculationcircuit;

[0032]FIG. 6 is a block diagram showing the configuration of aconventional neutral voltage controller;

[0033]FIG. 7 is a block diagram showing the configuration of a PWM pulsecalculator of a three-phase neutral-point-clamped inverter of a firstembodiment of the invention;

[0034]FIG. 8 is a block diagram showing the configuration of a neutralvoltage controller of a second embodiment of the invention;

[0035]FIG. 9 is a view showing an operation of a neutral voltagecontroller of a third embodiment of the invention; and

[0036]FIG. 10 is a block diagram showing the configuration of theneutral voltage controller of the third embodiment of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0037] Hereinafter, preferred embodiments of the invention will bedescribed with reference to the drawings. In the drawings, the samereference numerals denote the identical components.

[0038] First Embodiment

[0039] Next, a three-phase neutral-point-clamped PWM inverter apparatusof a first embodiment of the invention will be described with referenceto FIG. 7. FIG. 7 is a block diagram showing the configuration of a PWMpulse calculator of a three-phase neutral-point-clamped inverterapparatus of the embodiment. As shown in FIG. 7, the three-phaseneutral-point-clamped inverter apparatus of the embodiment comprises aneutral potential control parameter calculator 101, a vector timecalculator 102, a vector time register 103, and a PWM pattern settingdevice 104.

[0040] When the three-phase neutral-point-clamped inverter apparatus ofthe embodiment is to output an output voltage vector V, PWM pulses areoutput on the basis of vectors constituting the regions (regions 1 to 6)where the output voltage vector V exists, shown in FIG. 4. Assuming thatthe vectors constituting the regions are sorted as shown in FIG. 4, thevector time calculator 102 calculates total output times of the sortedvectors to output the output voltage vector V, as follows: total outputtime of zero-voltage vector T0 total output time of xp and xn vectors T1total output time of z vector T2 total output time of yp and yn vectorsT3 total output time of a vector T4 total output time of b vector T5.

[0041] The currents of the neutral line due to outputs of the vectorsare indicated as follows:

[0042] neutral current due to output of z vector: ic

[0043] neutral current due to output of xp and xn vectors: icx

[0044] neutral current due to output of yp and yn vectors: icy.

[0045] Measured values of U-, V-, and W-phase load current instantaneousvalues are indicated by i(U), i(V), and i(W), respectively. When thevectors are in the respective regions, i(phase1), i(phase2), andi(phase3) are changed respectively to i(U), i(V), and i(W) as shown inTable 2. Therefore, the neutral currents can be calculated by thefollowing expressions. In the expressions, phase1 is the phase when xpand xn vectors are output, phase2 is the phase when z vector is output,and phase3 is the phase when yp and yn vectors are output.

ic=i(phase2)×T2

icx=i(phase1)×T1

icy=i(phase3)×T3

[0046] When the neutral currents ic, icx, and icy are obtained in thisway, the neutral potential variation can be made close to zero bedetermining the time ratios of xp and xn, and yp an yn vectors so thatthe current variation of the neutral line is made close to zero by usingic, icx, and icy.

[0047] Hereinafer, an example of a specific method of calculating thetime ratios of the vectors will be described.

[0048] As described in JP-A-2001-57784, the parameter setting device 105uses neutral potential control parameters (α, α1, and α2 in the neutralpotential control. Relationships among the parameters are changeddepending on relationships between the region where the voltage vectorexists and the phase currents in the following manner:

[0049] when i(phase1)≧0, α1=α

[0050] when i(phase1)<0, α1=1−α

[0051] when i(phase3)≧0, α2=1−α

[0052] when i(phase3)<0, α2=α

[0053] (Note: a phase current which is directed from the inverter to amotor is positive.)

[0054] Table 1 below shows the correspondence among phase1, phase2, andphase3, and the U-, V-, and W-phases. (Table 1)

[0055] Correspondence Table of Phases Region phase1 phase2 phase3 1 U VW 2 V U W 3 V W U 4 W V U 5 W U V 6 U W V

[0056] Then, the time allocations of xp and xn vectors are set asfollows:

[0057] time of xp vector: Txp=α1×T2

[0058] time of xn vector: Txn=(1−α1)×T2,

[0059] and the time allocations of yp and yn vectors are set as follows:

[0060] time of yp vector: Typ=α2×T3

[0061] time of yn vector: Tyn=(1−α2)×T3.

[0062] The neutral potential control parameter α is calculated by aneutral potential control parameter calculator 106 as a sum of twoparameters α′ and α″ as follows:

α=α′+αα″ (0≦α≦1).

[0063] It is assumed that α is limited to a range of 0 or more to 1 orless.

[0064] Here, α′ is calculated in the following manner:

D=γ/(2×β)

[0065] α′=D (when ic≧0)

[0066] α′=−D (when ic<0)

[0067] (also α′ is limited to a range of 0 or more to 1 or less).

[0068] Furthermore, α″ is an offset adjustment parameter, and assumed tobe used for compulsively controlling the neutral potential in the caseof an abnormal neutral potential or the like, and to be usually 0.5.

[0069] Moreover, β and γ are obtained in the manner shown in (1) to (4)below.

[0070] (1) When |ic|<|icx|≦|icy| or |ic|<|icy|≦|icx|, α′ is calculatedwhile setting γ=ic and β=|icx|+|icy|.

[0071] (2) When |icx|≦|ic|≦|icy| or |icx|≦|icy|≦|ic|, α′ is calculatedwhile setting γ=|ic|−|icx| and β=|icy|. However, α1 is separately set inthe following manner:

[0072] when icx and ic have the same sign,

[0073] α1=1 is fixed, and

[0074] when icx and ic have different signs,

[0075] α1=0 is fixed.

[0076] (3) When |icy|≦|ic|≦|icx| or |icy|≦|icx|≦|ic|, α′ is calculatedwhile setting γ=|ic|−|icy| and β|icx|. However, α2 is separately set inthe following manner:

[0077] when icx and ic have the same sign,

[0078] α2=0 is fixed, and

[0079] when icy and ic have different signs,

[0080] α2=1 is fixed.

[0081] (4) When |icx|+|icy|≦|ic|,

[0082] when icx and ic have the same sign,

[0083] α1=1 is fixed,

[0084] when icx and ic have different signs,

[0085] α1=0 is fixed,

[0086] when icy and ic have the same sign,

[0087] α2=0 is fixed, and

[0088] when icy and ic have different signs,

[0089] α2=1 is fixed.

[0090] When the neutral potential control parameter α is calculated inthis way, the neutral potential variation due to the neutral currentwhich is caused to flow by z vector can be made close to zero as far aspossible for each PWM period, by efficiently using the neutral currentwhich is caused to flow by xp, xn, yp, and yn vectors.

[0091] Also in the method in which generation of z vector is suppressedas in the method described in JP-A-2001-061283, when T2 in the abovecalculation is set as the time elapsed after generation of the vector issuppressed, the neutral potential variation can be efficientlysuppressed while maintaining the above calculation as it is.

[0092] In the three-phase neutral-point-clamped PWM inverter apparatusof the embodiment, in consideration of the case where ic is so largethat compensation cannot be completely attained during the PWM perioddepending on the operation conditions of the inverter, such as the caseof |icx|+|icy|≦|ic|, compensation is performed in a slightly excessivedegree when

[0093] |icx|+|icy|≧|ic|, |icx|≧|ic|, and |icy|≧|ic|

[0094] are caused.

[0095] In order to realize the above, in the three-phaseneutral-point-clamped PWM inverter apparatus of the embodiment, a changemay be made so as to compensate the integral value of a current whichhas flown through the neutral line up to now, instead of compensation ofthe neutral current which is caused to flow by z vector during a PWMperiod. Specifically, a change may be made so that ic uses a sum of atime integral value ic0 of a neutral current which has flown before theprevious period, and the neutral current i(phase2) caused by z vector inthe next PWM period, as indicated by the following expression:

ic=ic0+i(phase2)×T2.

[0096] According to the configuration, it is possible to suppress theneutral potential variation which has not been sufficiently suppressedduring one period. The time integral value ic0 of the neutral currentmay be measured by a current sensor disposed on the neutral line, orcalculated by prediction based on the phase output currents coupled tothe neutral line.

[0097] In the case where the capacitances of series-connected smoothingcapacitors are equal to one another, when the neutral current is madeclose to zero as in the three-phase neutral-point-clamped PWM inverterapparatus of the embodiment, the neutral potential variation can be madezero, and the neutral potential can be controlled to the potential (thepotential is indicated by V0) which is exactly the middle between thepotentials of the positive and negative busses. In the case where thecapacitances of the series-connected capacitors are made different fromone another as a result of deterioration with time, even when theneutral current is made close to zero, however, the neutral potentialcannot be controlled to become the potential which is exactly the middlebetween the potentials of the positive and negative busses.

[0098] In the invention, therefore, instead that the neutral current ismade close to zero from the calculated values of ic, icx, and icy, theneutral current may be controlled so that the currently is converselyincreased so as to be close to V0. In this case, the neutral potentialcontrol parameter calculator 101 detects the level of the neutralpotential. If the potential is higher than V0, the neutral current canbe increased from the calculated values of ic, icx, and icy in thedirection of the arrow in FIG. 1, and, if the potential is lower thanV0, the neutral current can be increased in the direction opposite tothat of the arrow in FIG. 1.

[0099] Second Embodiment

[0100] The second neutral voltage controller of the invention will bedescribed. FIG. 8 is a block diagram showing the configuration of theneutral voltage controller of the embodiment. As shown in FIG. 8, theneutral voltage controller of the embodiment is configured by asubtracter 1, two comparators 2, a calculation circuit 3, and insulationcircuits 10.

[0101] The subtracter 1 outputs a value which is obtained by subtractingthe first reference voltage V_(ref1) from the neutral voltage V_(CN). Asdescribed above, the first reference voltage value V_(ref1) is one half(½·V_(PN)) of the voltage between the point P and the point N.

[0102] In the neutral voltage controller of the embodiment, in additionto the first reference voltage value V_(ref1), a second referencevoltage value V_(ref2) and a third reference voltage value V_(ref3) areused. As shown in FIG. 9, the second reference voltage value V_(ref2)and the third reference voltage value V_(ref3) are negative and positivevalues, respectively.

[0103] One of the comparators 2 turns on a signal for raising theneutral voltage and outputs the signal to the calculation circuit 3 whenthe value of the output of the subtracter 1 is smaller than the secondreference voltage value V_(ref2). The other comparator 2 turns on asignal for lowering the neutral voltage V_(CN) and outputs the signal tothe calculation circuit 3 when the value of the output of the subtracter1 is larger than the third reference voltage value V_(ref3).

[0104] The signals output from the two comparators 2 are input to theinsulation circuits 10 as a 2-bit digital signal, and then input to thecalculation circuit 3. Since the insulation circuits 10 are circuitswhich handle a digital signal, the circuits are not required to have alinear characteristic and the like in a wide range. Therefore, theinsulation circuits can be configured more economically than theisolation amplifiers 6 shown in FIG. 2.

[0105] The calculation circuit 3 receives the outputs of the twocomparators 2. When the signals from the two comparators 2 are notinput, the circuit maintains the neutral voltage as it is. When thesignal for raising the neutral voltage is input, the circuit produces aneutral voltage control command for raising the neutral voltage. Whenthe signal for lowering the neutral voltage is input, the circuitproduces a neutral voltage control command for lowering the neutralvoltage.

[0106] As described above, in the neutral voltage controller of theembodiment, the differences between the neutral voltage V_(CN) and thereference voltage values are converted from the analog signals to adigital signal. Therefore, the economical insulation circuits 10 whichhandle a digital signal can be used without using expensive insulationcircuits having a wide linear characteristic. As a result, the wholeapparatus can be economically configured.

[0107] In the neutral voltage controller of the embodiment, thedifferences between the neutral voltage V_(CN) and the reference voltagevalues are processed in the form of a digital signal instead of ananalog signal. Therefore, an influence of noises on the input to thecalculation circuit 3 can be reduced, so that the reliability of theapparatus can be enhanced, and a highly accurate neutral voltage controlis enabled.

[0108] In the neutral voltage controller of the embodiment, a dead bandis disposed with using the second reference voltage value V_(ref2) andthe third reference voltage value V_(ref3) as thresholds, therebyallowing the neutral voltage control to be performed without beingaffected by noises of a small level which are contained in the neutralvoltage. In the neutral voltage controller of the embodiment, moreover,it is preferable to set the thresholds due to the second referencevoltage value V_(ref2) and the third reference voltage value V_(ref3) soas to be wider the neutral voltage variation which occurs at a frequencythat is three times the frequency output by the three-level inverterapparatus. According to the configuration, the influence of noises canbe eliminated, and a usual variation component, i.e., a variationcomponent of a frequency which is thrice the operation frequency can beneglected. Therefore, simplification and high reliability of the controlcan be realized. The calculation circuit 3 may be configured bysoftware, or by hardware such as an electric circuit.

[0109] Third Embodiment

[0110] Next, a neutral voltage controller of a third embodiment of theinvention will be described with reference to FIG. 10. FIG. 10 is ablock diagram showing the configuration of the neutral voltagecontroller of the embodiment. As shown in FIG. 10, the neutral voltagecontroller of the embodiment is different from the neutral voltagecontroller of the above-described embodiment in that the controllercomprises a comparator 4 in place of the two comparators 2, and astorage device 5 instead of the calculation circuit 3.

[0111] The comparator 4 receives a value which is obtained bysubtracting the first reference voltage V_(ref1) from the neutralvoltage V_(CN), and outputs three 2-bit digital signals which havedifferent values in cases where the value of the output of thesubtracter 1 is smaller than the second reference voltage valueV_(ref2), where the output value is equal to or larger than the secondreference voltage value V_(ref2) and equal to or smaller than the thirdreference voltage value V_(ref3), and where the output value is largerthan the third reference voltage value V_(ref3).

[0112] The storage device 5 stores a plurality of tables of sets ofvalues of the digital signals and neutral voltage control commands whichare to be output at the values, in accordance with amotoring/regenerative operation of the inverter, or the operation statusof the inverter according to the use status. The storage device 5selects a table according to the present operation status, from thetables, and outputs a neutral voltage control command corresponding to adigital signal, with using the table.

[0113] Table 2 shows switching states and changes of the neutralvoltage. The switching states are switching patterns in the case where avector is to be output, such as shown in FIG. 4, and indicated in thesequence of the U-, V-, and W-phases. P indicates a state where thephase is connected to point P on the positive side, N indicates a statewhere the phase is connected to point N on the negative side, and Oindicates a state where the phase is connected to neutral point C.

[0114] As apparent from FIG. 4, for example, ap vector and an vector areequivalent to each other as a line voltage to be output, but aredifferent in switching state. With respect to a change of the neutralvoltage in a motoring operation, for example, the change in the case ofap vector is rising, and that in the case of an vector is lowering, orthe changes are opposite to each other. Also in motoring andregenerative operations, the changes of the neutral voltage are oppositeto each other. In this way, there are sets of voltage vectors in which,even when the line voltage to be output is identical, the neutralvoltage can be raised or lowered. Depending on which vector is selected,therefore, the neutral voltage can be controlled. In the neutral voltagecontroller of the embodiment, these relationships are stored in form ofa table, so that, with respect to variation of the neutral voltage, apattern which cancels the variation can be selected. TABLE 2 Change ofVoltage Switching neutral voltage vector state Motoring Regenerative 0pPPP Unchanged Unchanged 0o 000 Unchanged Unchanged 0n NNN UnchangedUnchanged a PNN, NPN, NNP Unchanged Unchanged b PPN, NPP, PNP UnchangedUnchanged c P0N, 0PN, NP0, Depending Depending N0P, 0NP, PN0 on phase onphase ap P00, 0P0, 00P Raising Lowering bp PP0, 0PP, P0P RaisingLowering an 0NN, N0N, NN0 Lowering Raising bn 00N, N00, 0N0 LoweringRaising

1. A three-phase neutral-point-clamped PWM inverter apparatus which hasa positive bus, a negative bus, and a neutral line, and in whichneutral-point-clamped PWM inverters for three phases are disposed, eachof said neutral-point-clamped PWM inverters being configured by:connecting in series first and second switch elements, and third andfourth switch elements between said positive bus and a phase voltageoutput terminal, and said negative bus and a phase output terminal,respectively; and connecting a node between said first and second switchelements, and a node between said third and fourth switch elements tosaid neutral point via respective clamp elements, characterized in thatsaid apparatus comprises: means for obtaining a first calculated valuewhich is a product of: a calculated value of a time of three-phaseoutput voltages in a state where said positive bus, said negative bus,and said neutral line are connected respectively to said three-phasephase output terminals during a PWM period; and a value of a currentwhich is predicted to flow through said neutral point in said state;means for obtaining a second calculated value which is a products of: acalculated value of a time of three-phase output voltages that can takea second state where two of said three-phase phase output terminals areconnected to said positive bus, and one of said three-phase phase outputterminals is connected to said neutral line, or a third state where twoof said three-phase phase output terminals are connected to said neutralline, and one of said three-phase phase output terminals is connected tosaid negative bus; and a value of a current which is predicted to flowthrough said neutral line in said state; means for obtaining a thirdcalculated value which is a products of: a calculated value of a time ofthree-phase output voltages that can take a fourth state where one ofsaid three-phase phase output terminals is connected to said positivebus, and two of said three-phase phase output terminals are connected tosaid neutral line, or a fifth state where one of said three-phase phaseoutput terminals is connected to said neutral line, and two of saidthree-phase phase output terminals are connected to said negative bus;and a value of a current which is predicted to flow through said neutralline in said state; and ratio determining means for determining ratiosof said second and third states, and said fourth and fifth states duringa PWM period so as to, on the basis of said first, second, and thirdcalculated values, make a current flowing through said neutral lineclose to zero, or a potential of said neutral line close to a potentialwhich is exactly a middle between potentials of said positive andnegative busses.
 2. A three-phase neutral-point-clamped PWM inverterapparatus according to claim 1, wherein, in place of said ratiodetermining means set froth in claim 1, ratio determining means obtainsa fourth calculated value which is a sum of said first calculated value,and an integral value of a current which has flown through said neutralline up to a PWM period preceding by one period, and determines ratiosof said second and third states, and said fourth and fifth states duringa PWM period so as to, on the basis of said second and third calculatedvalues, make said fourth calculated value close to zero, or, with usingsaid fourth calculated value, a potential of said neutral line close toa potential which is exactly a middle between potentials of saidpositive and negative busses.
 3. A three-phase neutral-point-clamped PWMinverter apparatus according to claim 1, wherein, in a three-phaseneutral-point-clamped PWM inverter apparatus in which a time ofthree-phase output voltages in six switch states where said positivebus, said negative bus, and said neutral line are connected respectivelyto said three-phase phase output terminals is suppressed to a firstpreset value or smaller, and an insufficient amount of an output voltageis compensated six switch states where each of said three-phase phaseoutput terminals is connected to said positive bus or said negative bus,and excluding a state where all of three of said three-phase phaseoutput terminals are concurrently connected to said positive bus or saidnegative bus, in place of said means for obtaining said first calculatedvalue set froth in claim 1, means obtains a first calculated value whichis a product of: the time of three-phase output voltages which aresuppressed to said first preset value or smaller during a PWM period;and a value of a current which is predicted to flow through said neutralpoint in said state.
 4. A three-phase neutral-point-clamped PWM inverterapparatus according to claim 3, wherein a measured value of a currentflowing through said neural line is used in place of said current whichis predicted to flow through said neutral point, and said ratiodetermining means obtains a fourth calculated value which is a sum ofsaid first calculated value, and an integral value of a current whichhas flown through said neutral line up to a PWM period preceding by oneperiod, and determines ratios of said second and third states, and saidfourth and fifth states during a PWM period so as to, on the basis ofsaid second and third calculated values, make said fourth calculatedvalue close to zero, or, with using said fourth calculated value, apotential of said neutral line close to a potential which is exactly amiddle between potentials of said positive and negative busses.
 5. Athree-phase neutral-point-clamped PWM inverter apparatus according toany one of claims 1 to 3, wherein, in said means for obtaining saidfirst to third calculated values, said value of said current which ispredicted to flow through said neutral point is calculated by using avalue of a current which is predicted to flow through said phase outputterminal connected to said neutral line.
 6. A neutral voltage controllerwhich controls a neutral voltage that is a voltage between a neutralpoint of two capacitors connected in series between positive andnegative busses of a three-level inverter apparatus, and said negativebus, characterized in that said neutral voltage controller comprises:subtracting means for outputting a value which is obtained bysubtracting a first reference voltage value from a value of said neutralvoltage, said first reference voltage value being one half of a voltagebetween said positive and negative busses; first comparing means for,when said value output from said subtracting means is smaller than asecond reference voltage value which is a negative value, turning on asignal for raising said neutral voltage; second comparing means for,when said value output from said subtracting means is larger than athird reference voltage value which is a positive value, turning on asignal for lowering said neutral voltage; insulating means forconverting said two signals to a 2-bit digital signal in an insulativemanner; and calculating means for, on the basis of said digital signal,calculating a neutral voltage control command, and outputting saidcommand.
 7. A neutral voltage controller which controls a neutralvoltage that is a voltage between a neutral point of two capacitorsconnected in series between positive and negative busses of athree-level inverter apparatus, and said negative bus, characterized inthat said neutral voltage controller comprises: subtracting means foroutputting a value which is obtained by subtracting a first referencevoltage value from a value of said neutral voltage, said first referencevoltage value being one half of a voltage between said positive andnegative busses; a comparator which outputs a 2-bit digital signalhaving different values in cases where said value output from saidsubtracting means is smaller than a second reference voltage value whichis a negative value, where said value output from said subtracting meansis larger than a third reference voltage value which is a positivevalue, and where said value output from said subtracting means is equalto or larger than said second reference voltage value and equal to orsmaller than said third reference voltage value; insulating means foroutputting said bit digital signal in an insulative manner; andcalculating means for, on the basis of said digital signal, calculatinga neutral voltage control command, and outputting said command.
 8. Aneutral voltage controller which controls a neutral voltage that is avoltage between a neutral point of two capacitors connected in seriesbetween positive and negative busses of a three-level inverterapparatus, and said negative bus, characterized in that said neutralvoltage controller comprises: subtracting means for outputting a valuewhich is obtained by subtracting a first reference voltage value from avalue of said neutral voltage, said first reference voltage value beingone half of a voltage between said positive and negative busses; firstcomparing means for, when said value output from said subtracting meansis smaller than a second reference voltage value which is a negativevalue, turning on a signal for raising said neutral voltage; secondcomparing means for, when said value output from said subtracting meansis larger than a third reference voltage value which is a positivevalue, turning on a signal for lowering said neutral voltage; insulatingmeans for converting said two signals in an insulative manner to a 2-bitdigital signal; and storage means for previously storing a table of setsof a value of said digital signal and a neutral voltage control commandwhich is to be output at said value, obtaining a neutral voltage controlcommand which corresponds to said digital signal supplied from saidinsulating means, from said table, and outputting said neutral voltagecontrol command.
 9. A neutral voltage controller which controls aneutral voltage that is a voltage between a neutral point of twocapacitors connected in series between positive and negative busses of athree-level inverter apparatus, and said negative bus, characterized inthat said neutral voltage controller comprises: subtracting means foroutputting a value which is obtained by subtracting a first referencevoltage value from a value of said neutral voltage, said first referencevoltage value being one half of a voltage between said positive andnegative busses; a comparator which outputs a 2-bit digital signalhaving different values in cases where said value output from saidsubtracting means is smaller than a second reference voltage value whichis a negative value, where said value output from said subtracting meansis larger than a third reference voltage value which is a positivevalue, and where said value output from said subtracting means is equalto or larger than said second reference voltage value and equal to orsmaller than said third reference voltage value; insulating means foroutputting said digital signal in an insulative manner; and storagemeans for previously storing a table of sets of a value of said digitalsignal and a neutral voltage control command which is to be output atsaid value, obtaining a neutral voltage control command whichcorresponds to said digital signal supplied from said insulating means,from said table, and outputting said neutral voltage control command.10. A neutral voltage controller according to claim 9, wherein saidstorage means stores a plurality of said tables corresponding tooperation statuses of an inverter, selects a table corresponding to apresent operation status, from said tables, and outputs a neutralvoltage control command corresponding to said digital signal with usingsaid table.
 11. A neutral voltage controller according to any one ofclaims 6 to 10, wherein a difference between said second and thirdreference voltage values is set to be larger than an amplitude ofneutral voltage variation at a frequency which is three times an outputfrequency of said three-level inverter.